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ADVANCE INFORMATION
CDC1651F-E Automotive Controller
Edition Jan. 27, 2005 6251-667-1AI
MICRONAS
CDC1651F-E
Contents Page 3 3 7 8 9 9 10 11 12 12 13 14 15 16 17 17 18 18 19 19 19 21 25 26 Section 1. 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.3. 3. 3.1. 3.2. 3.3. 3.4. 4. 5. 5.1. 6. 6.1. 7. 7.1. 7.2. 8. 8.1. 9. Title Introduction Features Abbreviations Block Diagram Package and Pins Package Outline Dimensions Pin Assignment External Components Electrical Data Absolute Maximum Ratings Recommended Operating Conditions Characteristics Recommended Crystal Characteristics CPU, RAM, ROM and Banking Core Logic Control Register CR Interrupt Controller (IR) Interrupt Assignment
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Hardware Options Functional Description Listing of Dedicated Addresses and Corresponding Hardware Options Register Cross-Reference Table Modified Registers Data Sheet History
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1. Introduction
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The device is a microcontroller for use in automotive applications. The on-chip CPU is a 65C816, an upgrade of the 65C02 with 16-bit internal data and 24-bit address bus. The chip consists of timer/counters, an interrupt controller, a multichannel A/D converter, a stepper motor and LCD driver, UARTs, a CAN interface and PWM outputs. This document provides ROM hardware-specific information. General information on operating the IC can be found in the document "CDC16xxF-E, Automotive Controller Family User Manual, CDC1605F-E Automotive Controller Specification" (6251-606-1PD).
1.1. Features
Table 1-1: CDC16xxF Family Feature List This device: Item Core CPU CPU-active operation modes Power-saving operation modes (CPU inactive) EMI reduction mode Oscillators RAM ROM 16-bit 65C816, featuring software compatibility with its 8-bit NMOS and CMOS 6502-series predecessors FAST, SLOW and DEEP SLOW WAKE and IDLE selectable in FAST mode 4 to 12 MHz quartz, RC 6 Kbyte ROMless, external program storage with up to 16 Mbyte, internal 2-Kbyte boot ROM 256-Kbyte Flash, bottom boot configuration, internal 2-Kbyte boot ROM 2 Kbyte 64 Kbyte 4 Kbyte 128 Kbyte, 2-Kbyte SF- ROM 4 to 12 MHz quartz FAST and SLOW CDC1605F-E EMU CDC1607F-E MCM Flash CDC1631F-E Mask ROM CDC1651F-E Mask ROM CDC1605F-C EMU CDC1607F-C MCM Flash CDC1641F-C Mask ROM CDC1652F-C Mask ROM CDC1672F-C Mask ROM
CDC1651F-E
6 Kbyte ROMless, external program storage with up to 16 Mbyte, internal 2-Kbyte boot ROM 256-Kbyte Flash, bottom boot configuration, internal 2-Kbyte boot ROM
2.75 Kbyte 90 Kbyte
4 Kbyte 128 Kbyte
6 Kbyte 216 Kbyte
3
Table 1-1: CDC16xxF Family Feature List, continued This device: Item Multiplier, 8 by 8 bit Digital watchdog Central clock divider Interrupt controller expanding NMI Port interrupts including slope selection Port wake-up inputs including slope / level selection Patch module Boot system CDC1605F-E EMU 16 inputs,15 priority levels 4 inputs 10 CDC1607F-E MCM Flash CDC1631F-E Mask ROM CDC1651F-E Mask ROM CDC1605F-C EMU CDC1607F-C MCM Flash CDC1641F-C Mask ROM CDC1652F-C Mask ROM CDC1672F-C Mask ROM
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CDC1651F-E
10 ROM locations allows in-system downloading of code and data into RAM via serial link
5 ROM locations -
10 ROM locations allows in-system downloading of code and data into RAM via serial link
5 ROM locations -
6 ROM locations
Analog Reset/Alarm Clock and supply supervision 10-bit ADC, charge balance type ADC reference Comparators LCD combined input for regulator input supervision 9 channels (5 channels selectable as digital input)
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VREF pin P06COMP with 1/2 AVDD reference internal processing of all analog voltages for the LCD driver
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Table 1-1: CDC16xxF Family Feature List, continued This device: Item Communication DMA UART Synchronous serial peripheral interfaces Full CAN modules V2.0B 1 DMA channel for serving the graphics bus interface 3: UART0, UART1 and UART2 2: SPI0 and SPI1 3: CAN0, CAN1 and CAN2 with 256-byte object RAM each (LCAN000F) 1 master module 1: UART0 1: SPI0 1 DMA channel for serving the graphics bus interface 2: UART0 and UART1 3: UART0, UART1 and UART2 1: UART0 1: SPI0 1: CAN0 with 256-byte object RAM (LCAN0009) 1 DMA channel for serving the graphics bus interface 3: UART0, UART1 and UART2 2: SPI0 and SPI1 2: CAN0 and CAN1 with 256-byte object RAM each (LCAN0009) 1 master module CDC1605F-E EMU CDC1607F-E MCM Flash CDC1631F-E Mask ROM CDC1651F-E Mask ROM CDC1605F-C EMU CDC1607F-C MCM Flash CDC1641F-C Mask ROM CDC1652F-C Mask ROM CDC1672F-C Mask ROM
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2: SPI0 and SPI1 3: CAN0, CAN1 and CAN2 with 256-byte object RAM each (LCAN0009) 1 master module
1: CAN0 with 256-byte object RAM (LCAN000F)
DIGITbus Input & Output Universal ports selectable as 4:1-mux LCD segment/ backplane lines or digital I/ O ports Universal port slew rate Stepper motor control modules with high-current ports 8-bit PWM modules
-
up to 52 I/O or 48 LCD segment lines (=192 segments), in groups of two, configurable as I/O or LCD
HW-preselectable 5 modules, 24 dI/dt-controlled ports
5 modules: PWM0, PWM1, PWM2, PWM3 and PWM4
3 modules: PWM0, PWM1, PWM2
5 modules: PWM0, PWM1, PWM2, PWM3 and PWM4
2 modules: PWM0, PWM1
5 modules: PWM0, PWM1, PWM2, PWM3 and PWM4
CDC1651F-E
Audio module with autodecay SW-selectable clock outputs
2
5
Table 1-1: CDC16xxF Family Feature List, continued This device: Item Polling/flash timer output Timers & Counters 16-bit free-running counters with capture/compare modules 16-bit timers 8-bit timers CCC0 with 3 CAPCOM CDC1605F-E EMU CDC1607F-E MCM Flash CDC1631F-E Mask ROM CDC1651F-E Mask ROM CDC1605F-C EMU CDC1607F-C MCM Flash CDC1641F-C Mask ROM CDC1652F-C Mask ROM CDC1672F-C Mask ROM
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CDC1651F-E
1 high-current port output operable in power-saving operation modes
1: T0 2: T1 and T2 -
Real-time clock, delivering hours, minutes and seconds Miscellaneous Scalable layout in CAN, RAM and ROM Various HW options selectable at random
-
mask-programmed according to user specification
-
mask-programmed according to user specification
most options SW-programmable, copy from user program storage during system startup 4.5 V to 5.5 V Tcase: 0 C to +70 C -
most options SW-programmable, copy from user program storage during system startup -
Core bond-out Supply voltage Temperature range Package Type Bonded pins
Tcase: -40 C to +105 C
Tamb: -40 C to +85 C
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ceramic 177PGA 176
PMQFP100-1 0.65 mm pitch 100
ceramic 177PGA 176
PMQFP100-1 0.65 mm pitch 100
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ADVANCE INFORMATION
CDC1651F-E
1.2. Abbreviations
ADC AM CAN CAPCOM CCC CPU DMA ERM IR LCD P06COMP PINT PSM PWM RTC SF-ROM SM SPI T UART Analog-to-Digital Converter Audio Module Controller Area Network Capture/Compare Capture/Compare Counter Central Processing Unit Direct Memory Access EMI Reduction Module Interrupt Controller Liquid Crystal Display P0.6 Alarm Comparator Port Interrupt Module Power-Saving Module Pulse Width Modulator Real-Time Clock Special-Function ROM Stepper Motor Control Module Serial Synchronous Peripheral Interface Timer Universal Asynchronous Receiver/Transmitter
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CDC1651F-E
1.3. Block Diagram
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VSS VDD
UVDD UVSS LCD Control U port 1
8
Reset/Alarm Test RESETQ TEST XTAL1 XTAL2 Watchdog Clock ERM RC Oscillator RTC Power Saving Module 16 Input Interrupt Controller Banking 8-bit Timer 1 65C816 CPU 8-bit Timer 2 U port 3 16-bit CAPCOM 1 16-bit CAPCOM 2 16-bit Timer 0 8 Patch Module DMA Logic U port 2 8
Audio Module U port 4 VREF AVDD AVSS P port 0
Multiplier, 8 by 8 bit
RAM 4K x 8
UART 0
8
9
10-bit ADC
H port 0
6
Clock Out 1 16-bit CAPCOM 0
U port 5
Stepper Motor Control
Special Function ROM 2K x 8
Clock Out 0
8
H port 1
6
8-bit PWM 2 8-bit PWM 0 ROM 128K x 8
UART 1
H port 2
CAN 0 SPI 0 SPI 1
U port 6
8
6
8-bit PWM 4
H port 3
6
8-bit PWM 1 8-bit PWM 3
U port 7
4
HVDD1 HVSS1 HVDD2 HVSS2
Fig. 1-1: CDC1651F-E block diagram
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CDC1651F-E
2. Package and Pins
2.1. Package Outline Dimensions
Fig. 2-1: PMQFP100-1: Plastic Metric Quad Flat Package, 100 leads, 14 x 20 x 2.7 mm3 Ordering code: QB Weight approximately 1.7 g
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CDC1651F-E
2.2. Pin Assignment
Pin Functions Port Port Special Out Special In GWRQ GRDQ Pin No. 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin No. 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
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Bus Mode
LCD Mode SEG7.3 SEG7.2 SEG7.1 SEG7.0
ADB7 ADB6 ADB5 ADB4 ADB3 ADB2 ADB1 ADB0
SEG3.7 T2-OUT SEG3.6 CC1-OUT SEG3.5 SPI1-CLK-OUT SEG3.4 T0-OUT SEG3.3 CC2-OUT SEG3.2 SEG3.1 CO1 SEG3.0 SPI1-D-OUT SEG6.7 CAN0-TX SEG6.6 PINT1-OUT SEG6.5 T1-OUT SEG6.4 SPI0-D-OUT
SPI1-CLK-IN WP0
SPI1-D-IN MULTI-TEST-IN CAN0-RX/WP1 SPI0-D-IN
SEG6.3 SEG6.2 SEG6.1 SEG6.0 WEQ SEG1.7 CEQ SEG1.6 ITSTOUT SEG1.5 RWQ SEG1.4 PH2 BP3 OEQ BP2 BE BP1 RDY BP0 STOPCLK VPQ VPA VDA DB7 DB6
SPI0-CLK-OUT T1-OUT LCD-CLK-OUT LCD-SYNC-OUT
SPI0-CLK-IN PINT2-IN/WP5 PINT1-IN/WP4 PINT0-IN/WP3 WP2
LCD-CLK-OUT LCD-SYNC-OUT
ITSTOUT SMB1+ SMB1SMB2+ SMB2SME1+/PWM2 SME1-/PWM0
SMB-COMP
DB5 DB4 DB3 DB2 DB1 DB0
SME2+ SME2SMA1+ SMA1SMA2+ SMA2-
SME-COMP
SMA-COMP
Basic Function U7.3 U7.2 U7.1 U7.0 UVSS UVDD U3.7 U3.6 U3.5 U3.4 U3.3 U3.2 U3.1 U3.0 U6.7 U6.6 U6.5 U6.4 TEST RESETQ XTAL2 XTAL1 VSS VDD U6.3 U6.2 U6.1 U6.0 U1.7 U1.6 U1.5 U1.4 U1.3 U1.2 U1.1 U1.0 H1.5 H1.4 H1.3 H1.2 H1.1 H1.0 HVDD1 HVSS1 H0.5 H0.4 H0.3 H0.2 H0.1 H0.0
100 1
91 90
81 80
30 31 40 41 50
51
NC = not connected, leave vacant
Basic Function U4.0 U4.1 U4.2 U4.3 U4.4 U4.5 U4.6 U4.7 U5.0 U5.1 U5.2 U5.3 U5.4 U5.5 U5.6 U5.7 U2.0/GD0 U2.1/GD1 U2.2/GD2 U2.3/GD3 U2.4/GD4 U2.5/GD5 U2.6/GD6 U2.7/GD7 AVSS AVDD VREF P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9 H2.0 H2.1 H2.2 H2.3 H2.4 H2.5/Pol HVSS2 HVDD2 H3.0 H3.1 H3.2 H3.3 H3.4 H3.5
Port Special In WP7
Pin Functions Port Special Out SME1+ SME1-
UART0-RX/WP8 CC2-IN CC1-IN CC0-IN INT-TEST-IN LCD-CLK-IN LCD-SYNC-IN IRQ ABORTQ PINT3/WP6 PINT3/UART1-RX UART0-TX CC1-OUT CO1 CC0-OUT AM-PWM AM-OUT UART1-TX CO0 PWM2 PINT0-OUT
LCD Mode SEG4.0 SEG4.1 SEG4.2 SEG4.3 SEG4.4 SEG4.5 SEG4.6 SEG4.7 SEG5.0 SEG5.1 SEG5.2 SEG5.3 SEG5.4 SEG5.5 SEG5.6 SEG5.7 SEG2.0 SEG2.1 SEG2.2 SEG2.3 SEG2.4 SEG2.5 SEG2.6 SEG2.7
Bus Mode ADB8 ADB9 ADB10 ADB11 ADB12 ADB13 ADB14 ADB15
ADB16 ADB17 ADB18 ADB19 ADB20 ADB21 ADB22 ADB23
P0.1 digital input P0.2 digital input P0.3 digital input P0.4 digital input P0.5 digital input P0.6 Compar. inp.
SMC-COMP
WP9
SMC2SMC2+ SMC1SMC1+ PWM0 PWM4
SMD-COMP
PWM1 PWM3 SMD2SMD2+ SMD1SMD1+
Fig. 2-2: Pin Assignment for PMQFP100-1 Package
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CDC1651F-E
2.3. External Components
C = 100 n to 150 n +5 V L VDD C = 100 n to 150 n C VSS 18 p C XTAL1 HVSS 1 to 2 HVDD 1 to 2 2xC +5 V
UVDD
System Ground
+5 V Analog
IC
AVDD +5 V 18 p 4.7 k 47 n XTAL2 VREF 10 n C
Resetq System Ground
RESETQ
UVSS
AVSS
Analog Ground
Fig. 2-3: Recommended external supply and quartz connection for low electromagnetic interference (EMI) To provide effective decoupling and to improve EMC behavior, the small decoupling capacitors must be located as close to the supply pins as possible. The self-inductance of these capacitors and the parasitic inductance and capacitance of the interconnecting traces determine the self-resonant frequency of the decoupling network. A frequency too low will reduce decoupling effectiveness, increase RF emissions and may affect device operation adversely. XTAL1 and XTAL2 quartz connections are especially sensitive to capacitive coupling from other printed circuit board signals. It is strongly recommended to place quartz and oscillation capacitors as close to the pins as possible and to shield the XTAL1 and XTAL2 traces from other signals by embedding them in a VSS trace. The RESETQ pin adjacent to XTAL2 should be supplied with a 47 nF capacitor, to prevent fast RESETQ transients from being coupled into XTAL2, to prevent XTAL2 from coupling into RESETQ, and to guarantee a time constant of 200 s, sufficient for proper Wake Reset functionality.
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CDC1651F-E
3. Electrical Data
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3.1. Absolute Maximum Ratings
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute maximum ratings conditions for extended periods will affect device reliability. This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum-rated voltages to this high-impedance circuit. Table 3-1: All voltages listed are referenced to ground (UVSS = HVSSn = AVSS = 0 V), except where noted. All ground pins except VSS must be connected to a low-resistive ground plane close to the IC. Symbol VSUP Parameter Core supply voltage Port supply voltage Analog supply voltage SM supply voltage 1 SM supply voltage 2 Voltage difference between VDD and AVDD, resp. UVDD Core supply current Port supply current Analog supply current SM supply current @Tj = 105 C, duty factor = 0.71 1) Input voltage Pin Name VDD UVDD AVDD HVDD1 HVDD2 VDD, AVDD UVDD VDD, VSS UVDD, UVSS AVDD, AVSS HVDD1, HVSS1 HVDD2, HVSS2 U ports, XTAL,RESETQ, TEST P0 ports VREF H ports Iin Io Input current Output current all inputs U ports H ports toshsl Tj Ts Pmax
1)
Min. -0.3
Max. 6.0
Unit V
VDD ISUP IASUP IHSUP Vin
-0.5 -100 -20 -380 UVSS - 0.5
0.5 100 20 380 UVDD + 0.7
V mA mA mA V
UVSS - 0.5 HVSS - 0.5 0 -5 -60
AVDD + 0.7 HVDD + 0.7 2 5 60 indefinite
V V mA mA mA s C C W
Duration of short circuit in Port SLOW mode to UVSS or UVDD Junction temperature under bias Storage temperature Maximum power dissipation
U ports except U3.2 in DP mode -45 -45
115 125 0.8
This condition represents the worst case load with regard to the intended application
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CDC1651F-E
3.2. Recommended Operating Conditions
Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. Keep UVDD = AVDD during all power-up and power-down sequences. Failure to comply with the above recommendations will result in unpredictable behavior of the device and may result in device destruction. Functional operation of the device beyond those indicated in the "Recommended Operating Conditions" of this specification is not implied, may result in unpredictable behavior of the device and may reduce reliability and lifetime. Table 3-2: All voltages listed are referenced to ground (UVSS = HVSSn = AVSS = 0 V), except where noted. All ground pins except VSS must be connected to a low-resistive ground plane close to the IC. Symbol VDD Parameter Supply voltage Port supply voltage Analog supply voltage SM supply voltage 1 SM supply voltage 2 Voltage difference between VDD and AVDD resp. UVDD AVDD ripple, peak-to-peak XTAL clock frequency XTAL clock frequency using ERM Vil Low input voltage Pin Name VDD UVDD AVDD HVDD1 HVDD2 VDD, AVDD UVDD AVDD XTAL1 XTAL1 U ports H ports P0 ports TEST U ports H ports P0 ports TEST RESETQ RESETQ 0.86 x VDD 4 4 Min. 4.5 Typ. 5 Max. 5.5 Unit V
HVDD VDD dAVDD fXTAL
4.75 -0.2
5
5.25 0.2 200 12 10 0.51 x VDD
V V mV MHz MHz V
Vih
High input voltage
V
RVil WRVil
Reset active input voltage Reset active input voltage during power-saving modes and Wake Reset Reset inactive and Alarm active input voltage Reset inactive and Alarm inactive input voltage Reset inactive during powersaving modes ADC reference input voltage P0 ADC input port input voltage
0.9 0.6
V V
RVim RVih WRVih VREFi P0Vi
RESETQ RESETQ RESETQ VREF P0 ports
1.6 2.9 UVDD - 0.4 V 2.56 0
2.1
V V V
AVDD VREFi
V V
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CDC1651F-E
3.3. Characteristics
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Listed are only those characteristics that differ from chapter 3.3 of document "CDC16xxF-E, Automotive Controller Family User Manual, CDC1605F-E Automotive Controller Specification" (6251-606-1PD). All not differing characteristics, that are not listed here, apply, but in a TCASE temperature range extended to -40 C to +105 C. Table 3-3: UVSS = HVSS1 = HVSS2 = AVSS = 0 V, 4.5 V < VDD = AVDD = UVDD < 5.5 V, 4.75 V < HVDD1 = HVDD2 < 5.25 V, TCASE = -40 C to +105 C, fXTAL = 10 MHz. Symbol Package Rthjc Rthja Thermal resistance from junction to case Thermal resistance from junction to ambient 12.1 41.0 K/W K/W measured on Micronas typical 2-layer board, 1s1p, described in document "Integrated Circuits - Thermal Characterization of Packages" (6200266-1E) (modified JESD-51.3) Parameter Pin Name Min. Typ. 1) Max. Unit Test Conditions
Supply Currents (CMOS levels on all inputs, no loads on outputs, difference between any two VDDs within 0.2 V) IDDF IDDS VDD FAST mode supply current VDD SLOW mode supply current VDD DEEP SLOW mode supply current VDD IDLE mode supply current VDD VDD 35 1.5 65 2.0 mA mA all modules off 2) 3), all hardware options set to their reset values all modules off 2) 3), all hardware options set to their reset values fxtal = 4 MHz 3) fxtal = 10 MHz 3) internal RC oscill.
IDDD
VDD
0.75
1.0
mA
IDDI
VDD
70 180 12
135 260 55 50 0.3
A A A A mA mA mA A A A
IDDW UIDDa AIDDa
VDD WAKE mode supply current UVDD active supply current AVDD active supply current
VDD UVDD AVDD
0
1
no output activity, LCD module on ADC on, ERM off ERM on, fXTAL = 8.4 MHz ADC and ERM off no output activity, LCD module off no output activity, SM module off
0.2 1
0.4 2 10 10 20
AIDDq UIDDq HIDDq
Quiescent supply current
AVDD UVDD sum of all HVDDn
0 0 0
1 1 1
1) Typical values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical recommended operating conditions applied, and are not 100% tested).
Value may be exceeded with unusual hardware option setting Measured with external clock. Add 100 A at 4 MHz, 115 A at 10 MHz for operation on typical quartz with SR3.XTAL = 0 (Oscillator RUN mode).
2) 3)
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CDC1651F-E
3.4. Recommended Crystal Characteristics
See chapter 3.4 of document "CDC16xxF-E, Automotive Controller Family User Manual, CDC1605F-E Automotive Controller Specification" (6251-606-1PD).
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CDC1651F-E
4. CPU, RAM, ROM and Banking
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Alternative
phys.addr. [H] 000000 log.addr. [H] 0000
Native
log.addr. [H] 000000
4 KB RAM
001000 001900 001A00 001B00 001C00 001D00 001E00 001F00 002000
Reserved
CAN0-RAM CAN-Regs Ext. I/O I/O-Reg1 I/O-Reg0 Bank 0
Bank 0 128 KB ROM
7FFF 8000
Bank 1
00F800 010000
SF-ROM
FFFF
8000
00FFFF
010000
Bank 2
FFFF 8000
Bank 1
Bank 3
FFFF 8000 022000
01FFFF 020000
Bank 4 Reserved
FFFF 8000
Bank 2
Bank 5
FFFF 8000 02FFFF 030000
Bank 6 Bank 3 Bank 15 Bank 7
080000 082000 FFFF 8000 07FFFF 080000
mirrored ROM
Bank 16
FFFF 8000
Bank 8
FFFFFF
Fig. 4-1: Address Map
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CDC1651F-E
5. Core Logic
5.1. Control Register CR
The control register CR serves to configure the ways by which certain system resources are accessed during operation. The main purpose is to obtain a variable system configuration during IC test. Upon each high transition on the RESETQ pin, internal hardware reads data from the address location 00FFF3h and stores it to the CR. The state of the TEST pin at that time specifies which program storage source is accessed for this read: Table 5-1: Control byte source 1 TEST 0 or NC 1 Control byte source x internal SF-ROM (standard for stand-alone operation) external, via multifunction pins in bus mode (for test purposes only) SFROM IROM 1 x normal mode normal mode MFM Multifunction Pin Mode (Table 5-2)
Table 5-2: TSTTOG and MFM usage TSTTOG 0 1 MFM 0 0 TEST pin x 0 Multifunction Pins bus mode bus mode
SF-ROM (Table 5-3) Internal ROM (Table 5-3)
Table 5-3: SFROM and IROM usage The system will thus start up according to the configuration defined in address location 00FFF3h, automatically copied to register CR. SFROM 1 CR
7 6
IROM 1
selected program storage internal ROM internal SF-ROM
Control Register
5
x
0
2
IROM
4
MFM
3
SFROM
1
IRAM
0
ICPU Res
x
0
r/w RESLNG TSTTOG
external via multifunction pins in bus mode
Value of 00FFF3h
IRAM r/w1: r/w0: ICPU r/w1: r/w0:
Internal RAM Enable internal RAM. Disable internal RAM. Internal CPU Enable internal CPU. Disable internal CPU.
RESLNG Reset Pulse Length r/w1: Pulse length is 16/FXTAL r/w0: Pulse length is 4096/FXTAL This bit specifies the length of the reset pulse which is output at pin RESETQ following an internal reset. If pin TEST is 1 the first reset after power on is short. The following resets are as programmed by RESLNG. If pin TEST is 0, all resets are long. TSTTOG TEST Pin Toggle (Table 5-2) This bit is used for test purposes only. If TSTTOG is true in IC active mode, pin TEST can toggle the multifunction pins between bus mode and normal mode.
Table 5-4: Some commonly used settings for address location 00FFF3h. A copy is automatically transferred to the CR when exiting reset. Code FFh ABh TEST Pin 0 1 Operation Mode Stand-alone with internal ROM External program storage connected to multifunction pins in bus mode
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CDC1651F-E
6. Interrupt Controller (IR)
Listed are only those registers that differ from document "CDC16xxF-E, Automotive Controller Family User Manual, CDC1605F-E Automotive Controller Specification" (6251606-1PD).
ADVANCE INFORMATION
Table 6-4: INT-MUX 6= HW Option addr. FFC1H
bit 3 0 bit 2 0 1 0 1 selects Timer 2 VSS VSS PINT2-IN
6.1. Interrupt Assignment
(cf. chapter 10.3 in "CDC16xxF-E, Automotive Controller Family User Manual, CDC1605F-E Automotive Controller Specification" (6251-606-1PD))
0 1 1
Table 6-1: INT-MUX 1 = HW Option addr. FFC0H
bit 1 0 0 1 1 bit 0 0 1 0 1 selects CC0 COMP Timer 2 VSS Timer 1
Table 6-5: INT-MUX 9= HW Option addr. FFC2H
bit 1 0 0 1 1 bit 0 0 1 0 1 selects VSS UART 1 IR-RTC IR-WAPI
Table 6-2: INT-MUX 2 = HW Option addr. FFC0H
bit 3 0 0 1 1 bit 2 0 1 0 1 selects VSS P06 COMP SPI 0 Timer 1
Table 6-3: INT-MUX 4 = HW Option addr. FFC0H
bit 7 0 0 1 1 bit 6 0 1 0 1 selects VSS SPI 0 DMA PINT3-IN
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CDC1651F-E
7. Hardware Options
7.1. Functional Description
Hardware options are available in several areas to adapt the IC function to the host system requirements: - clock signal selection for most of the peripheral modules from fosc to fosc/217 plus some internal signals (see "Table 25-2: Clock Option Selection Code" in Chapter "25. Hardware Options" of document "CDC16xxF-E, Automotive Controller Family User Manual, CDC1605F-E Automotive Controller Specification" (6251-606-1PD)). - interrupt source selection for interrupt inputs 0, 1, 5, 6, 7, 10, 13, 14 and 15 - Special-out signal selection for some U and H ports - Rx/Tx polarity selection for SPI and UART modules - U Port Slow mode selection In ROM parts, hardware options are not software-programmable. The data in address locations 00FFA0H through 00FFC3H were used to define their respective, hard-wired hardware options during mask production and can only be altered by changing a production mask for this IC. For verification purposes, it is recommended to have an application code in ROM that runs with Flash parts as well which is automatically the case if Flash parts have been used for software development and tests before. This implies reading of locations 00FFA0h through 00FFC3h directly after reset, to activate the hardware options' settings in Flash and EMU parts as well.
7.2. Listing of Dedicated Addresses and Corresponding Hardware Options
Listed are only those registers that differ from document "CDC16xxF-E, Automotive Controller Family User Manual, CDC1605F-E Automotive Controller Specification" (6251606-1PD).
Table 7-1: Hardware-Option-Dedicated Addresses (cf. chapter 25.2 in "CDC16xxF-E, Automotive Controller Family User Manual, CDC1605F-E Automotive Controller Specification" (6251-606-1PD)) 7 00FFB4 UART0 Tx 0: direct 1: inverted 00FFC0 Mux4: 00 01 10 11 00FFC1 Mux8: 00 01 10 11 CC1OR PINT2-IN IR-RTC IR-WAPI VSS SPI 0 DMA PINT3-IN 6 5 4 3 2 1 0
UART0 Input and Output UART0 Rx 0: direct 1: inverted x x x x x x
Interrupt Sources Multiplexer 1 to 4 Mux3: 00 01 10 11 PINT3-IN SPI 1 UART 1 CC1 COMP Mux2: 00 01 10 11 VSS P06 COMP SPI 0 Timer 1 Mux1: 00 01 10 11 CC0 COMP Timer 2 VSS Timer 1
Interrupt Sources Multiplexer 5 to 8 Mux7: 00 01 10 11 CC0OR UART 1 IR-RTC IR-WAPI Mux6: 00 01 10 11 Timer 2 VSS VSS PINT2-IN Mux5: 00 01 10 11 Timer 2 UART 1 SPI 1 DMA
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Table 7-1: Hardware-Option-Dedicated Addresses, continued (cf. chapter 25.2 in "CDC16xxF-E, Automotive Controller Family User Manual, CDC1605F-E Automotive Controller Specification" (6251-606-1PD)) 7 00FFC2 H-Port 1.1 0: SME 1: PWM2 6 5 4 3 2 1 0
Interrupt Sources Multiplexer 9 and Port Multiplexer x H-Port 1.0 0: SME 1: PWM0 PINT3-IN 0: at U5.6 1: at U5.7 x x Mux9: 00 01 10 11 VSS UART 1 IR-RTC IR-WAPI
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CDC1651F-E
8. Register Cross-Reference Table
Table 8-1: CAN RAM, memory page 1B
Address (hex) 1B00 ... 1BFF Mnemonic CAN0_RAM Block CAN0-RAM
Table 8-3: I/O Registers, memory page 1E
Address (hex) 1E64 1E65 1E66 Mnemonic PAR0 PAR1 PAR2 PDR PER0 PER1 WUS Power-Saving Module Block Patch Module
Table 8-2: CAN Registers, memory page 1C
Address (hex) 1C00 1C01 1C02 1C03 1C04 1C05 1C06 1C07 1C08 1C09 1C0A 1C0B 1C0C 1C0D 1C0E 1C0F 1C10 1C11 CAN0BT1 CAN0BT2 CAN0BT3 CAN0ICR CAN0OCR CAN0TEC CAN0REC CAN0ESM CAN0CTIM Mnemonic CAN0CTR CAN0STR CAN0ESTR CAN0IDX CAN0IDM Block
1E67 1E68 1E69
CAN0
1E70 1E71 1E74 1E75 1E76 1E78 1E79 1E7A 1E7C 1E7D 1E7E 1E80 1E81 1E82 1E83 1E84 1E88 1E90 1E94 1E98 1E99 1E9C
SSR
SSC
RTC
WPM0 WPM2 WPM4 WPM6 WPM8 WSC OSC RTCC POL
SMX
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CDC1651F-E
Table 8-3: I/O Registers, memory page 1E, continued
Address (hex) 1EA0 1EA1 1EA2 1EA3 Mnemonic MULCAND MULPLIER MULPROD Block Multiplier
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Table 8-4: I/O Registers, memory page 1F, continued
Address (hex) 1F1F 1F20 1F21 1F22 1F23 Mnemonic IRE IRC IRRET IRPRI10 IRPRI32 IRPRI54 IRPRI76 IRPRI98 IRPRIBA IRPRIDC IRPRIFE IRP IRPM0 IRPP AMAS AMF AMDEC U2D U2SEG10 U2M10 U2SEG32 U2M32 U2SEG54 U2M54 U2SEG76 U2M76 TIM0 Timer 0 Universal Port 2 Audio Module Block Interrupt Controller
Table 8-4: I/O Registers, memory page 1F
Address (hex) 1F00 1F01 1F02 1F08 1F09 1F0A 1F0B 1F0C 1F0F 1F10 1F11 1F12 1F13 1F14 1F15 1F18 1F19 1F1A 1F1B 1F1C 1F1D 1F1E Mnemonic CSW0 CR ERMC SR0 SR1 SR2 SR3 DBG ABR SPI0D SPI0M SPI1D SPI1M CO0SEL CO1SEL UA1D UA1C UA1BR0 UA1BR1 UA1IM UA1CA UA1IF UART1 Core Logic SPI1 Debug Register Memory Banking SPI0 ERM Core Logic Block Core Logic
1F24 1F25 1F26 1F27 1F28 1F29 1F2A 1F2B 1F2C 1F2D 1F2E 1F2F 1F30 1F32 1F33 1F34 1F35 1F36 1F37 1F38 1F39 1F4E 1F4F 1F50 1F51 1F52
PWM0 PWM1 PWM2
PWM
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CDC1651F-E
Table 8-4: I/O Registers, memory page 1F, continued
Address (hex) 1F88 1F89 Stepper Motor Module 1F8A 1F90 1F91 1F92 PWM 1F98 1F99 Core Logic 1F9A 1F9B Capture Compare Module 1F9C 1F9D 1F9E 1F9F Mnemonic H2NS H2TRI H2D H3NS H3TRI H3D U1D U1SEG10 U1SEG32 U1M30 U1SEG54 U1M54 U1SEG76 U1M76 UA0D UA0C UA0BR0 UA0BR1 UA0IM UA0CA UA0IF AD0 AD1 U3D U3SEG10 U3M10 U3SEG32 U3M32 U3SEG54 U3M54 U3SEG76 U3M76 Universal Port 3 AD Converter UART0 Universal Port 1 High Current Port 3 Block High Current Port 2
Table 8-4: I/O Registers, memory page 1F, continued
Address (hex) 1F54 1F55 1F5A 1F5B 1F5C 1F5D 1F5E 1F5F 1F60 1F61 1F6C 1F6D 1F6E 1F6F 1F70 1F71 1F72 1F73 1F74 1F75 1F76 1F77 1F7C 1F7D 1F7E 1F80 1F81 1F82 1F84 1F85 1F86 P0PIN H0NS H0TRI H0D H1NS H1TRI H1D High Current Port 1 Analog Input Port 0 High Current Port 0 CCC CC2M CC2I CC2 CC1M CC1I CC1 Mnemonic TIM1 TIM2 SMVC SMVSIN SMVCOS SMVCMP PWM3 PWM4 CSW1 CSW2 CC0M CC0I CC0 Block Timer 1, 2
1FA0 1FA1 1FA2 1FA3 1FA4 1FA5 1FA6 1FA8 1FA9 1FAC 1FAE 1FAF 1FB0 1FB1 1FB2 1FB3 1FB4 1FB5
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CDC1651F-E
Table 8-4: I/O Registers, memory page 1F, continued
Address (hex) 1FB8 1FBA 1FBB 1FBC 1FBD 1FBE 1FBF 1FC0 1FC1 1FC4 1FC6 1FC7 1FC8 1FC9 1FCA 1FCB 1FCC 1FCD 1FD0 1FD2 1FD3 1FD4 1FD5 1FD6 1FD7 1FD8 1FD9 1FDC 1FDE 1FDF 1FE0 1FE1 Mnemonic U4D U4SEG10 U4M10 U4SEG32 U4M32 U4SEG54 U4M54 U4SEG76 U4M76 U5D U5SEG10 U5M10 U5SEG32 U5M32 U5SEG54 U5M54 U5SEG76 U5M76 U6D U6SEG10 U6M10 U6SEG32 U6M32 U6SEG54 U6M54 U6SEG76 U6M76 U7D U7SEG10 U7M10 U7SEG32 U7M32 Universal Port 7 Universal Port 6 Universal Port 5 Block Universal Port 4
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Table 8-4: I/O Registers, memory page 1F, continued
Address (hex) 1FE8 1FE9 1FEA 1FEB 1FEC 1FED 1FEE 1FEF 1FFD 1FFE 1FFF TST3 TST1 TST2 TST DEA Mnemonic DCS DIC DSA Block DMA
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CDC1651F-E
8.1. Modified Registers
Listed are only those registers that differ from document "CDC16xxF-E, Automotive Controller Family User Manual, CDC1605F-E Automotive Controller Specification" (6251606-1PD).
8.1.1. Standby Registers
(cf. chapter 6.3 in "CDC16xxF-E, Automotive Controller Family User Manual, CDC1605F-E Automotive Controller Specification" (6251-606-1PD))
SR0
7
r/w SM 0
Standby Register 0
6
PWM1 0
5
PWM0 0
4
x x
3
SPI1 0
2
CAN0 0
1
CCC 0
0
SPI0 0 Res
SR2
7
r/w TIM2 0
Standby Register 2
6
PWM3 x
5
PWM2 0
4
UART1 x
3
PWM4 x
2
x x
1
EXTIR 0
0
ABM 0 Res
SR3
7
r/w x x
Standby Register 3
6
x x
5
x x
4
XTAL 1
3
WAID 0*)
2
FCLO 0
1
x x
0
x x Res
*)
Reset with pin reset or VDD power on
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9. Data Sheet History
1. "CDC1651F-E Automotive Controller", Jan. 27, 2005, 6251-667-1AI. First release of the advance information. Originally created for the HW version CDC1651F-E1.
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Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-667-1AI
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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